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vhdlsystem-verilogverificationformal-verification

Is there a way to ignore combinational loop error in HDL code?

I am trying to formally verify a small module in a very big Project code. I have anayzed and elaborated the design. I cannot verify the small module because the tool gives me a "Found Combinational Loop" error.

I am quite sure that this small module is not affected by this Loop error. So i want to avaid getting this error. Is it even possible?

Thanks!

Solution

  • Not sure what tool you used, in JasperGold formal tool, you can use following command setting to break a combinational loop.

    stopat u_DUT.signal_a

    Just put it before prove -all in your tcl file (if you uses a tcl file to run your tool).

    Have a look at stopat command in JapserGold manual for further information in your cases to see if you can easily break the comb loop.