PAD symbol "r<3>" has an undefined IOSTANDARD - Verilog

Question

I was writing Booth Multiplier code in Verilog.
I'm getting the following errors.

PAD symbol "r<3>" has an undefined IOSTANDARD
PAD symbol "r<3>" is not constrained (LOC) to a specific location.

I Don't want to test it in FPGA. Just need to stimulate in Xilinx ISE. So I did not write the ucf file.

Even though I'm getting this error, my stimulation is working perfectly.

1. Is ucf file always necessary?
2. How will I fix this?

The error doesn't let me generate the programming file.
Here is my code. (r used statements are commented)

module boothMulti( r, q, product 
    );
    input [3:0] r, q;           // Declaration of r[r shows error.]
    output reg [7:0] product;
    reg [8:0] a, b, p;
    reg [5:0] c;
    integer i;

    always@(q or r) begin       // r used here
        a[0]=0;
        b[0]=0;
        p[0]=0;

//setting up c
        c[0]=0;
        c[4:1]=r;               // r used here

//setting up a
        a[4:1]=q[3:0];
        a[8:5]=4'b0000;
        if(q[3]==0) begin a[8:5]=4'b0000; end
        else begin a[8:5]=4'b1111; end

//setting up b
        b[4:1]=((~q)+4'b0001);
        if(b[4]==0) begin b[8:5]=4'b0000; end
        else begin b[8:5]=4'b1111; end

//setting up p
        p[8:1]=8'b00000000;

    for( i=1; i<5; i=i+1) begin         
        case({c[i],c[i-1]})
            2'b0_0:begin
                    a=a<<<1; b=b<<<1;
                    end
            2'b0_1:begin
                    p=p+a;
                    a=a<<<1; b=b<<<1;
                    end
            2'b1_0:begin
                    p=p+b;
                    a=a<<<1; b=b<<<1;
                    end
            2'b1_1:begin
                    a=a<<<1; b=b<<<1;
                    end
            endcase
        end                 //end for loop
        product[7:0]=p[8:1];
    end                     //end always@
endmodule

Answer 1

I just simulated this design successfully: it compiled and ran for a bit, but, bearing in mind you did not post a testbench, everything was x. I also managed to generate a programming file.

How about

• quitting from ISE,
• restarting,
• closing the project and
• creating a completely new project?

There may be something lurking in your existing project that is causing this.