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initializationvhdlresetflip-flop

VHDL flip-flop reset different than 0

is any possibility to reset flip-flop vector to different value than all 0? something like:

PROCESS (clk)
    BEGIN
        IF RISING_EDGE(clk) THEN
            IF rst = '1' THEN
                ff <= INPUT_VALUE;
...

This don't survive synthesis. I want to get the value to ff only when resetting, then I'm changing it - it works as a counter with first value set from input.

Solution

  • How about implementing a normal reset and then use load signal to set the counter to something else? This to me would be the standard way.