I am working on fixing a broken project. One of the things which I came across in the process was that there where many declared but never used signals, which led me to this question!
Would the synthesiser waste hardware resources by implementing these declared but unused signals or would it just ignore them?
The synthesis itself is a very complex task. The synthesizer has to map the logic you want, on the structures you provide to him. So for an FPGA he has to do something else then for standart cells. During this task, he optimizes. A lot! It tries to get rid of unused signals. It can also optimize your finite automata. It is a very powerful tool.
But don't forget that synthesis is complicated. So is the programming of hardware behavior. It is usually a good idea to perform a linting step before the synthesis. The linting tool provides you with information about your design. It automatically detects error prone code, wrong reset behavior. With linting, you can locate some code, which might be problematic later on.
TL;DR Yes, synthesizer can trim out your unused logic and connections. It does way more. But be careful about it. It may backfire.