Declaring task in same verilog file

Question

I'm trying to declare a simple clock wiggle task in a testbench, but ModelSim is claiming that no design element of my task's type exists. What's the problem with this code:

`timescale 1 ns/1 ns

module at25320a_tester();
    reg clk, s_in, s_out, chip_select, write_protect, hold;

    // Instantiate at25320a module
    at25320a EEPROM (.SCK(clk), .SI(s_in), .CSNeg(chip_select), .HOLDNeg(hold), .WPNeg(write_protect), .SO(s_out));

    run_clk(15);

    task run_clk;
        input [3:0] cycles;
        output reg clk;

        integer i;

        for (i=0;i<cycles;i=i+1) begin
            #100 clk = 1;
            #100 clk = 0;
        end
    endtask

endmodule 

Answer 1

Tasks must be called from a procedural block, such as always or initial. In your case, youll want to run the task in an initial block with a few modifications:

`timescale 1 ns/1 ns

module at25320a_tester();
    reg clk, s_in, s_out, chip_select, write_protect, hold;

    // Instantiate at25320a module
    at25320a EEPROM (.SCK(clk), .SI(s_in), .CSNeg(chip_select), .HOLDNeg(hold), .WPNeg(write_protect), .SO(s_out));

    initial begin
        run_clk(15);
    end

    task run_clk;
        input integer cycles; // Might as well not have this be bigger
        // No clock, you want to use the clock from the module
        integer i;

        for (i=0;i<cycles;i=i+1) begin
            #100 clk = 1;
            #100 clk = 0;
        end
    endtask

endmodule