how do I represent negative decimal verilog

Question

I have converted some decimal values into fixed point and want to carry out some multiplication, however some of these values are negative can anyone show me an easy way to carry out the multiplication I have tried this but had no success:

pix_r2m<=($signed({1'b0,pix_rld})*8'b11101101;// the binary is:-0.148.

This is happening in a synchronous manner and pix_r2m, pix_rld are defined as :

reg [16:0]pix_r2m;
reg [7:0]pix_rld;

Answer 1

Verilog given any opportunity will revert to unsigned arithmetic, here the multiplicand or coefficient is unsigned. Telling it is signed with 8'sb, allows correct sign extension to take place.

module test;
  reg [16:0]pix_r2m;
  reg [7:0]pix_rld;

  always @* begin
    //* -0.148
    pix_r2m = $signed({1'b0,pix_rld}) * 8'sb11110111;
  end

  initial begin
    pix_rld = {4'd1,4'd0}; //1
    #1 $display("%b", pix_r2m);


    pix_rld = {4'd2,4'd0}; //2
    #1 $display("%b", pix_r2m);
  end


endmodule

EDA Playground.

But you likely want the result to be flagged as signed so you should be using :

reg signed [16:0]pix_r2m;