Using VHDL Record in SystemVerilog Testbench in Modelsim

Question

I've done research on this, but the examples that I've found on other web pages have broken links. I'm looking for an example of how to import a custom VHDL record that is contained in a package into a SystemVerilog Testbench.

I'm using modelsim, so I've read that I need to use the -mixedsvvh switch. Do I need to use this switch for both vcom and vlog calls? Also, there's another switch [b | s | v] which when I use s it gives me an error:

** Error: (vcom-1276) Option '-mixedsvvh' was given with a bad argument.

When I use no arguments, I try to run vsim and I get the following message:

-- Importing package c:/Projects/source/work.test_pkg__mti__sv__equiv__implct__pack ** Error: Test_Top_TB.sv(4): 't_Test' is an unknown type.

VHDL Package:

library ieee;
use ieee.std_logic_1164.all;
package test_pkg is
  type t_Test is record
    DATA1 : std_logic_vector(15 downto 0);
    DV1   : std_logic;
    DATA2 : std_logic_vector(5 downto 0);
    DV2   : std_logic;
  end record t_Test;
end package test_pkg;

VHDL Entity/Architecture:

library ieee;
use ieee.std_logic_1164.all;

library work;
use work.test_pkg.all;

entity Test_Top is
  port (
    i_Clk  : in  std_logic;
    i_Data : in  t_Test;
    o_Data : out t_Test
    );
end entity Test_Top;

architecture RTL of Test_Top is
begin
  process (i_Clk) is
  begin
    if rising_edge(i_Clk) then
      o_Data.DATA1 <= i_Data.DATA1;
      o_Data.DV1   <= i_Data.DV1;
      o_Data.DATA2 <= i_Data.DATA2;
      o_Data.DV2   <= i_Data.DV2;  
    end if;
  end process;
end architecture RTL;

SystemVerilog Testbench:

interface Test_IF();
  import test_pkg::*;

  t_Test Data;
endinterface // Test_IF

module Test_Top_TB ();
  import test_pkg::*;
  logic r_Clock;
  Test_IF hook();
  Test_IF hook2();
  Test_Top UUT 
    (.i_Clk(r_Clock),
     .i_Data(hook.Data),
     .o_Data(hook2.Data)
     );
endmodule

Answer 1

Try changing t_Test in your systemverilog testbench to lower case, ie. t_test.