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vhdlmodelsimquartus

VHDL - Testbench internal signals

I am spending some time learning about writing test benches to try out on some of the models I have produced. Does anyone know a way to monitor signals that are internal to the architecture of the unit under test. I have tried using 

LIBRARY MODELSIM_LIB;
USE MODELSIM_LIB.UTIL.ALL;
    spy_process : process begin
        init_signal_spy("Q4/C1/A1/chip_sel","/chip_sel",1);
        wait;
        end process spy_process;

But I get a compiler error of the :

Error (10481): VHDL Use Clause error at Q4.vhd(15): design library "MODELSIM_lib" does not contain primary unit "util"

I've checked the Quartus II library folder and util is there in the correct place. Any suggestions? Thanks D

Solution

  • When you start a simulation, Quartus analyzes all files specified in the project settings (accessible via menu Assignment -> Settings -> Files). But, it elaborates only the entities which are required for the DUT starting from the top-level entity (see menu Assignment -> Settings -> General) to find out which design files (excluding testbenches) are required for simulation. For more details, see my other answer.

    The library MODELSIM_LIB is found by ModelSim only, not by Quartus. Thus, Quartus-II fails to analyze your testbench file with the error posted in the question. But this is actually not required because it (should) only contain testbench code. Thus:

    1. remove this testbench file from your Quartus project via menu Project -> "Add/Remove Files in Project...", and
    2. add this file only in the simulation settings accessible via menu Assignment -> Settings -> Simulation -> Compile test bench -> Test Benches -> New/Edit.