Hello guys I am trying to translate following vhdl code to verilog however it does not work even if they look like pretty same. I get no errors however it is not working with verilog one but works with vhdl one. Can you guys please help me to work out this problem. :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity binbcd8 is
port(
b: in unsigned(7 downto 0);
p: out unsigned(9 downto 0)
);
end binbcd8;
architecture Behavioral of binbcd8 is
begin
bcd1: process(b)
variable z: unsigned(17 downto 0);
begin
for i in 0 to 17 loop
z(i):='0';
end loop;
z(10 downto 3):=b;
for i in 0 to 4 loop
if z(11 downto 8)>4 then
z(11 downto 8):=z(11 downto 8)+3;
end if;
if z(15 downto 12)>4 then
z(15 downto 12):=z(15 downto 12)+3;
end if;
z(17 downto 1):=z(16 downto 0);
end loop;
p<=z(17 downto 8);
end process;
end Behavioral;
to Verilog code and here is my code but it does not work. Can you please help me?:
module binbcd8(input[7:0] b,output reg[9:0] p);
reg[17:0] z;
integer i;
always@(b)
begin
z <=17'b0;
z[10:3] <=b;
for(i=0;i<4;i=i+1) begin
if(z[11:8]>4)
z[11:8]<=z[11:8]+3;
else
z<=z;
if(z[15:12]>4)
z[15:12]<=z[15:12]+3;
else
z<=z;
z[17:1]<=z[16:0];
end
p<=z[17:8];
end
endmodule
Your main problem is likely to be (a) that the VHDL loops 5 times (0 to 4) while the Verilog loops 4 times (for(i=0; i<4;...), and (b) that the Verilog code uses non-blocking assignments on z, where it should use blocking (z = x, not z <= x). Ask separately about that if you don't understand it.
Both sets of code could do with cleaning up. In the Verilog, your first assignment to z assigns 17 bits, not 18. The z <= z assignments are unnecessary. The VHDL uses a bizarre method to clear z - try variable z: unsigned(17 downto 0) := (others => '0');.