Search code examples
vhdlvariable-assignment

Aggregate assignment in VHDL using smaller aggregates

Is there a way to write something like this:

x <= (2 downto 0 => y(2 downto 0), others => y(3));

instead of this:

x <= (2 => y(2), 1 => y(1), 0 => y(0), others => y(3));

Thanks.

Solution

  • It's a good idea to show declarations. It's possible to answer based on the expectation your second aggregate in an assignment to x works.

    lasplund's comment on your question that it should work is predicated to IEEE Std 1076-2008 compatibility in which slices in aggregates were added. (See Peter Ashenden and Jim Lewis's book VHDL 2008 Just the New Stuff, 6.4 Slices in Aggregates).

    Support varies by VHDL tool implementation, usually a command line or configuration option to provide -2008 support. Previous revisions of the standard only followed your apparently working alternative with single element associations.

    See 1076-2008 8.5 Slice names and 9.3.3.3 Array aggregates.