How to delete useless registers generated by Chisel verilog backend?

Question

When I synthesize a verilog module generated by Chisel, I've got this type of warnings (a lot !) :

Warning (10036): Verilog HDL or VHDL warning at Polynomial.v(26): object "T98" assigned a value but never read

Is there an option to delete this type of "useless" signals when I generate the verilog code ?

I generate verilog with this option in scala code :

object PolynomialMain {
  def main(args: Array[String]): Unit = {
    chiselMain(Array("--backend", "v"), () => Module(new Polynomial()))
  }
}

And here my built.sbt :

libraryDependencies += "edu.berkeley.cs" %% "chisel" % "2.3-SNAPSHOT"

scalaVersion := "2.11.6"

scalacOptions ++= Seq("-deprecation",
                      "-feature",
                      "-unchecked",
                      "-language:reflectiveCalls")

Answer 1

I don't think so (not yet, that is).

Chisel punts a lot of the heavy lifting onto the lower-level tools. For example, your synthesis tools will happily ignore extra, unused registers, and it makes Chisel simpler to not do the analysis itself.

However, this is definitely something that should be addressed in the future, as it's bad form to generate code with so many warnings!