I'm new to FPGA, When I tried to implement my decoder on zynq-7000 clg484, there is an error,saying that:
Bitgen:342 - This design contains pins which have locations (LOC) that are not user-assigned or I/O Standards (IOSTANDARD) that are not user-assigned. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you may apply the following bitgen switch: -g UnconstrainedPins:Allow
And I tried to add -g UnconstrainedPins:Allow, still not working, saying that the 'clk' pin is not optimal, but seriously, I don't know which pin number is the general clock pin number!
Where can I find a document explain the pin number of the board ? I couldn't find it so I don't know which button on the board mapping to which number, so in PlanAhead(I/o pin planning), I always don't know which number to locate.
Your board is a ZedBoard, not a XC7Z020-clg484 which is the Zynq core of your board (the chip under the black heat sink). And the schematics of the ZedBoard are available on the web site. First check your board revision: look at the bar code sticker between the Zynq core and the FMC connector. Just below you should see a "REV C" or "REV D" white on green label. Next, go to http://zedboard.org/, Support -> Documentation -> ZedBoard -> Schematics and download the schematics of your revision. All you need is there. If you want to know what pin of the Zynq drives LD0 (the rightmost of the 8 user LEDs near the 8 switches), search for LD0. You will see that it is driven by pin T22 of bank 33 of the Zynq and that this bank has a 3.3V voltage. In order to automate the mapping of your I/Os to the pins of the Zynq you can use a TCL script like this one:
array set ios {
"gpi[0]" { "F22" "LVCMOS25" }
"gpi[1]" { "G22" "LVCMOS25" }
"gpi[2]" { "H22" "LVCMOS25" }
"gpi[3]" { "F21" "LVCMOS25" }
"gpi[4]" { "H19" "LVCMOS25" }
"gpi[5]" { "H18" "LVCMOS25" }
"gpi[6]" { "H17" "LVCMOS25" }
"gpi[7]" { "M15" "LVCMOS25" }
"gpo[0]" { "T22" "LVCMOS33" }
"gpo[1]" { "T21" "LVCMOS33" }
"gpo[2]" { "U22" "LVCMOS33" }
"gpo[3]" { "U21" "LVCMOS33" }
"gpo[4]" { "V22" "LVCMOS33" }
"gpo[5]" { "W22" "LVCMOS33" }
"gpo[6]" { "U19" "LVCMOS33" }
"gpo[7]" { "U14" "LVCMOS33" }
"srst" { "P16" "LVCMOS25" }
}
foreach io [ array names ios ] {
set pin [ lindex $ios($io) 0 ]
set std [ lindex $ios($io) 1 ]
set_property package_pin $pin [get_ports $io]
set_property iostandard $std [get_ports [list $io]]
}
In this example, we have one 8-bits input bus (GPI), one 8-bits output bus (GPO) and one single bit input (SRST). GPI is mapped to the 8 switches of the ZedBoad, GPO to the 8 LEDs and SRST to the centre button of the 5 press-buttons pad. As you can see gpo[0] is mapped to T22, the LED I mentioned above, and its iostandard property is LVCMOS33 (3.3 V). Adapt to your own I/O names and functions. Save the TCL script (foo.tcl) and run it just after you synthesised your design and before you implement it: menu Tools -> Run TCL script... if you use the GUI, else you know already. Have fun.