How to route array signal to input

Question

I have a top-level VHDL module that includes a signal that I declare to be an array of unsigned numbers. I have an instantiated component within this top-level module, and I want to route the array in the top-level module to this component. Making the same declaration of

type array_type is array(5 downto 0) of unsigned (15 downto 0);

in the component doesn't seem to work. I already know how to connect inputs to outputs containing arrays, but I'm not sure how to connect a signal to an input/output.

EXAMPLE TOP-LEVEL MODULE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity top_level is
end top_level;

architecture str_arch of top_level is
   type array_type is array (5 downto 0) of unsigned (15 downto 0);
   signal example_array: array_type;
begin
instantiated_component: entity work.component(Behavioral)
   port map(array=>example_array);
end str_arch;

Answer 1

1) declaring somewhere:

type array_type is array(5 downto 0) of unsigned (15 downto 0);

and in another place:

type array_type is array(5 downto 0) of unsigned (15 downto 0);

declares two different types ! even if they have the same name (they will have a full extended name: somewhere.array_type and another.array_type )

2) VHDL is a strongly typed language and even if the two different "types" you declared have the same definition you can't assign one to another.

One easy solution is to use the same type (from a package):

package pkg is
  type array_type is array(5 downto 0) of unsigned (15 downto 0);
end package pkg;

And in the sub-module and to-level modules:

use work.pkg.all; --if pkg is in the same library