I'm writing a VHDL code for a TFT LCD 7" screen by terasic and I'm having a hard time understand the timing specifications presented in the datasheet
I've found at a computer in my office a VHDL code ment for the same LCD screen and the guy who wrote it isn't availble. The most interesting part but yet not fully clear of the code he wrote is presented:
process(Reset,clk_33)
begin
if Reset = '0' then
H_count <= 0;
V_count <= 0;
DE <= '0';
LCD_fin <= '0';
R<=(others=>'0');
G<=(others=>'0');
B<=(others=>'0');
elsif rising_edge(clk_33) then
H_count <= H_count + 1; -- Horizantal pixels count
case V_count is -- Vertical row
when 0 to 12 => V_sync <= '0'; LCD_fin <= '0'; -- Vertical pulse width
when 13 to 22 => V_sync <= '1'; -- Vertical back porch
when 23 to 502 => V_sync <= '1'; -- Vertical valid
when 503 to 523 => V_sync <= '1'; LCD_fin <= '1'; -- Vertical front porch
when 524 => V_count <= 0;
end case;
case H_count is -- Horizontal column
when 0 to 29 => H_sync <= '0'; -- Horizontal pulse width
when 30 to 45 => H_sync <= '1'; -- Horizontal back porch
when 46 to 845 => H_sync <= '1'; DE<='1'; -- Horizontal valid
when 846 to 1054 => H_sync <= '1'; DE<='0';-- Horizontal front porch
when 1055 => H_count <= 0; V_count <= V_count + 1;
end case;
I know VHDL pretty good but I can't seem to find a good explenation for the items:
HSYNC/VSYNC setup/hold time[ns]
Horzontal/Vertical pulse width
In addition, do you have any idea why would there be 2 operation modes(DE/SYNC)? And when should I use each one? Modules for other types of screens such as VGA are much simpler..
My boss is pushing me hard on this task because I'm working on this for a month now. If somebody here will have a nice definition of these time parameters I will be more than happy :)
HSYNC/VSYNC setup/hold time[ns]
That's the minimal amount of time needed for the 33[mhz] DCLK to rise from '1' to '0' and vise versa.
Horzontal/Vertical pulse width
For LCD_HSD for example, that's the amount of DCLK's pulses in which LCD_HSD is high as 'tollin' mentioned. And the same for LCD_VSD for LCD_HSD as DCLK.
I've uploaded a repository to github with an LCD-driver quartus project that creates a comfortable generic module for everyone to use:
https://github.com/Doron-Behar/VEEK-MT_LCD-driver