Can someone please tell me the difference between <= and >= in VHDL?I know its greater than/less than or equal to sign.Can someone be precise and explain with a code of line how the execution takes place.I know usually for signal assignment we use <= but for example in state machines or whenever we use WHEN >= pops out.Can someone please tell me the difference?
There is a difference writing these in if-statements and elsewhere.
When using these in if-statements a mathematical operation is taking place. As you wrote a comparision is done, checking if value is great-or-equal, smaller-or-equal to the value you compare to.
When writing codes outside of the if-statements this are part of the VHDL syntax and has no mathematical meaning, it is just how the languagre is constructed.
signal_a <= signal_b -- Assign signal B to signal A
-- When something is A then do whats is inside when block
case something is
when A =>
-- Do some stuff
when others =>
-- Do other stuff
end case;