I have a STD_LOGIC_VECTOR (0 to 639).
On an incoming signal I have to iterate through this vector and get next 2 bits of it.
I'm trying to make something like, with an integer counter:
counter := counter+1;
MyVar := Data((counter*2) to ((counter*2)+1));
I get the following:
Error (10394): VHDL error at module.vhd(227): left bound of range must be a constant
upd: the following was suggested by @user1155120: writing every single bit of vector to every single corresponding bit of MyVar
MyVar(0) := Data(counter * 2);
MyVar(1) := Data(counter * 2 + 1);
Works fine as long as I use the 2bit MyVar, but what if i want to use a 16-32-80bit variable? Problem avoided, but not solved.
Googling shows the error message is from Quartus II (See ID: 10394). The LRM reference it provides isn't particularly helpful, it's a limitation on synthesis that you can't define a variable width word size for a multiplexer. Not smart enough to detect both bounds are referenced to counter.
What happens if you express a multiplexer for each bit of MyVar separately? (Indexed name instead of slice name, two variable assignments to MyVar(1) and MyVar(0)).
MyVar(0) := Data(counter * 2);
MyVar(1) := Data(counter * 2 + 1);
This thread need a help with strange error" left bound of the range must be a constant " suggests using a loop to assign each bit of the target slice range, which is also using an indexed name on a per element basis.
for i in MyVar'RANGE loop
MyVar(i) := Data(counter * 2 + i);
end loop;
counter only needs half the index range, you're always multiplying it by 2.