During synthesis, should I care about the "found latch" warnings if I actually want the latches?

Question

say I have the following state machine:

....
if state_a then
    output_a <= '0';
    next_state <= state_b;
elsif state_b then
    output_a < '0';
    if cond then
        output_b <= '1';
        next_state <= state_a;
    else
        next_state <= state_b;
    end if;
 end if;
 ......

I don't want output_b to change except when being assigned again in state_b. However, when I try to synthesise this code, most synthesis tools will say something along this line:

warning: found 1-bit latch for signal "output_b". latches aren't recommended for FPGA design because it might result in timing problems.

Should I worry about this at all? If so, why and what are the alternatives?

Answer 1

Following Xilinx:

If latch inference is intended, you can safely ignore this message. However, some inefficient coding styles can lead to accidental latch inference. You should analyse your code to see if this result is intended.

Some techniques to avoid latch inference:

• Make sure any "if / else if" statements have a concluding "else" clause,
• Assign to all the same outputs in each case,
• Include all possible cases in the case statement (but be aware that WHEN OTHERS clause always works, but can create extraneous logic).