I was attempting to implement a dual port RAM as guided in this excellent blog post. However, ModelSim is giving the following warning when compiling:
** Warning: fifo_ram.vhdl(24): (vcom-1236) Shared variables must be of a protected type.
I also seem unable to create this as a wave, indicating to me that the variable is not being recognised using my code below.
How can I correctly declare this variable as a "protected" type? Also, as a more general question about shared variables - is this variable shared between all entities in a design?
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity fifo_ram is
generic (data : natural := 8;
addr : natural := 16);
port (w_clk : in std_logic;
w_en : in std_logic;
w_addr : in std_logic_vector (addr-1 downto 0);
w_data : in std_logic_vector (data-1 downto 0);
--
r_clk : in std_logic;
r_rdy : in std_logic;
r_addr : in std_logic_vector (addr-1 downto 0);
r_data : out std_logic_vector (data-1 downto 0));
end fifo_ram;
architecture rtl of fifo_ram is
-- shared memory
type mem_type is array ( (2**addr) - 1 downto 0 ) of std_logic_vector(data-1 downto 0);
shared variable mem : mem_type;
begin
write: process (w_clk)
begin
if (rising_edge(w_clk)) then
if (w_en = '1') then
mem(conv_integer(w_addr)) := w_data;
end if;
end if;
end process write;
end architecture;
----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity tb_fifo is
generic (data : natural := 8;
addr : natural := 16);
end entity;
architecture testbed of tb_fifo is
signal tb_w_clk, tb_w_en : std_logic := '0';
signal tb_w_addr : std_logic_vector (addr-1 downto 0);
signal tb_w_data : std_logic_vector (data-1 downto 0);
signal tb_r_clk, tb_r_rdy : std_logic := '0';
signal tb_r_addr : std_logic_vector (addr-1 downto 0);
signal tb_r_data : std_logic_vector (data-1 downto 0);
begin
dut : entity work.fifo_ram(rtl)
port map(tb_w_clk, tb_w_en, tb_w_addr, tb_w_data,
tb_r_clk, tb_r_rdy, tb_r_addr, tb_r_data);
wclock : process is
begin
tb_w_clk <= '1';
wait for 10 ns;
tb_w_clk <= '0';
wait for 10 ns;
end process wclock;
wdata : process is
begin
tb_w_addr <= x"FFFF";
tb_w_data <= x"AA";
wait for 100 ns;
tb_w_en <= '1';
wait for 70 ns;
tb_w_en <= '0';
wait;
end process wdata;
end architecture;
OK, having gone through the blog post I now understand why they're using shared variable instead of signals. Its because multiple processes are assigning to this variable, which is not possible in the case of a reg in Verilog or a signal in VHDL. In that case the synthesizer will produce an error complaining of multiple drivers for mem. But in order to use shared variable in this case, you'll have to declare it as protected. What you need to do is declare a protected data type, and then encapsulate your mem variable inside it, much like classes in object oriented languages. Here's an example of the protected data type:
type mem_envelope is protected -- protected type declaration
variable mem : mem_type;
function GetVal( addr : integer ) return std_logic_vector(data - 1 downto 0);
function SetVal( addr : integer; val : std_logic_vector(data - 1 downto 0) ) return boolean; --may be used to indicate whether write was successfull or not
end protected mem_envelope;
Then declare a sharede variable of type mem_envelope and use GetVal and SetVal functions to read/write values to the memory inside your processes.