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vhdl

Array with dynamic length for simulation

In VHDL, is there a way to have a dynamically sized array for simulation?

I would like to use it as a list, i.e., the testbench repeatedly appends values to the end, and then iterates over the list. The length of the array is not statically known.

Solution

  • The array utility of VUnit (https://github.com/VUnit/vunit/tree/master/vunit/vhdl/array) provides the functionality you're looking for. It provides a protected type array_t which has a method append that does the dynamic sizing. Here is some code from the testbench for this utility (https://github.com/VUnit/vunit/blob/master/vunit/vhdl/array/test/tb_array.vhd) that exemplifies the append method

    variable arr : array_t;
...
arr.init;
...
arr.append(11);
check_equal(arr.length, 1);
check_equal(arr.get(0), 11);

arr.append(7);
check_equal(arr.length, 2);
check_equal(arr.get(1), 7);