I use ISE 14.7 and use vhdl design a cpu. when maping:
Blockquote Pack:2309 - Too many bonded comps of type "IOB" found to fit this device. Pack:18 - The design is too large for the given device and package. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. NOTE: An NCD file will still be generated to allow you to examine the mapped design. This file is intended for evaluation use only, and will not process successfully through PAR. This mapped NCD file can be used to evaluate how the design's logic has been mapped into FPGA logic resources. It can also be used to analyze preliminary, logic-level (pre-route) timing with one of the Xilinx static timing analysis tools (TRCE or Timing Analyzer).
This is my cup entity:
entity cpu is port (
RST : in std_logic;
CLK : in std_logic;
ABUS : out std_logic_vector(15 downto 0);
DBUS : inout std_logic_vector(15 downto 0);
nMREQ : out std_logic;
nRD : out std_logic;
nWR : out std_logic;
nBHE : out std_logic;
nBLE : out std_logic;
nPRD : out std_logic;
nPWR : out std_logic;
nPERQ : out std_logic;
IOAD : out std_logic_vector(1 downto 0);
IODB : inout std_logic_vector(7 downto 0);
ir : out std_logic_vector(15 downto 0) ;
tABUS : out std_logic_vector(15 downto 0);
tDBUS : out std_logic_vector(15 downto 0);
tnMREQ : out std_logic;
tnRD : out std_logic;
tnWR : out std_logic;
tnBHE : out std_logic;
tnBLE : out std_logic);
signal tmpABUS : std_logic_vector(15 downto 0);
signal tmpnMREQ : std_logic;
signal tmpnRD : std_logic;
signal tmpnWR : std_logic;
signal tmpnBHE : std_logic;
signal tmpnBLE : std_logic;
signal tmpnPRD : std_logic;
signal tmpnPWR : std_logic;
signal tmpnPERQ : std_logic;
end entity; -- cpu
in design summary: I use 129 IOBs,but total is 158. Where is my wrong? Thanks. And sorry for my English.
I am so foolish!!!
I just move the declaration of signals in entity to architecture.
And everything is OK, though I do not know why some IOBs errors will happens.
Thanks all.