Search code examples
vhdlverilogfpgaxilinxvivado

I cannot get the Xilinx uartlite IP to work


Im attempting to use the Xilinx uartlite 2.0 IP with an AXI4-lite interface to transmit a byte without a microblaze processor. Unfortunately, all the ready signals remain low after I set the data and valid signals and the tx signal never transmits.

I've included my simulation results. any ideas?

Xilinx Uartlite 2.0 axi4-lite timing simulation


Solution

  • For posterity, Had to invert the reset and ensure all the inputs were initialized. Thank you for the helpful comments. I've attached a working simulationenter image description here