How to assign pins to natural type of ports in Xilinx

Question

How can I assign natural types of ports to pins in XILINX UCF file?

Generic (
    nr_ro     : natural := 32
);            

Port (  
    clk_i     : in  STD_LOGIC;
    rst_i     : in  STD_LOGIC;
    sel1_i    : in  natural range 0 to nr_ro-1;
    sel2_i    : in  natural range 0 to nr_ro-1;
    bit_o     : out std_logic;
);

Answer 1

Unfortunately, the one place where you can't use type natural is top level ports, where they are mapped to physical device pins. This is because you need to connect each individual bit of the signal to its own pin, so you need some type that represents the signal as an array of bits.

My choice would be to convert to/from natural to unsigned for this purpose. The unsigned will have 5 bits to count from 0 to 31.

library ieee;
use ieee.numeric_std.all;
...

Port (  
          sel1    : in unsigned(nr_bits-1 downto 0);
...

sel_1 <= to_unsigned(sel1_i,nr_bits);
...

And now you connect each bit of sel_1 to its own pin in the UCF file. In VHDL you can access individual bits sel1(4), sel1(0) etc.

In the UCF file the syntax may be slightly different' sel1_4 etc, refer to the UCF documentation to see how it numbers individual bits of a bus..