I want to design 5 behavioral model for OR gate. What is the difference between these models? Each of models implement which of delays (inertial delay and transport delay) and what is the reason?
Model 1: LHS blocking
#4 O = (A | B);
Model 2: LHS non-blocking
#4 O <= (A | B);
Model 3: RHS blocking
O = #4 (A | B);
Model 4: RHS non-blocking
O <= #4 (A | B);
Model 5: Continuous assignment
assign #4 O = (A | B);
There is a very good paper "Correct Methods For Adding Delays To Verilog Behavioral Models" by Clifford E. Cummings, where you can find some hints about using different delay models in Verilog:
Blocking assignment delay models:
Modeling Guideline: do not place delays on the LHS of blocking assignments to model combinational logic. This is a bad coding style.
Testbench Guideline: placing delays on the LHS of blocking assignments in a testbench is reasonable since the delay is just being used to time-space sequential input stimulus events.
RHS blocking delays:
Modeling Guideline: do not place delays on the RHS of blocking assignments to model combinational logic. This is a bad coding style.
Testbench Guideline: do not place delays on the RHS of blocking assignments in a testbench.
General Guideline: placing a delay on the RHS of any blocking assignment is both confusing and a poor coding style. This Verilog coding practice should be avoided.
Nonblocking assignment delay models:
Modeling Guideline: do not place delays on the LHS of nonblocking assignments to model combinational logic. This is a bad coding style.
Testbench Guideline: nonblocking assignments are less efficient to simulate than blocking assignments; therefore, in general, placing delays on the LHS of nonblocking assignments for either modeling or testbench generation is discouraged.
RHS nonblocking delays:
Recommended Application: Use this coding style to model behavioral delay-line logic.
Modeling Guideline: place delays on the RHS of nonblocking assignments only when trying to model transport output-propagation behavior. This coding style will accurately model delay lines and combinational logic with pure transport delays; however, this coding style generally causes slower simulations.
Testbench Guideline: This coding style is often used in testbenches when stimulus must be scheduled on future clock edges or after a set delay, while not blocking the assignment of subsequent stimulus events in the same procedural block.
Continuous assignment delay models:
RHS delay model is illegal with continuous assignment
Models mentioned earlier model following delays: