how do i initialize a std_logic_vector in VHDL?

i have a std_logic_vector(4096 downto 0) Signal and i want to initialize it like below:

architecture Behavioral of test is

    type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0);
    signal ram : ram_type;
    ram(0) := "0010000000000100";   
    ram(1) := "0001000000000101";
    ram(2) := "0011000000000110";
    ram(3) := "0111000000000001";
    ram(4) := "0000000000001100";
    ram(5) := "0000000000000011";
    ram(6) := "0000000000000000";
    ram(4095 downto 7) := (others => (others => '0'));
    begin
   "some code"
end behavioral

for some reason i need to initialize it with these values (i can't assign these values to it , it has to be initialized) is there even any ways to do it? i tried the above code and it didn't work

Solution

The ram can be initialized like:

architecture Behavioral of test is
    type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0);
    signal ram : ram_type := (0 => "0010000000000100",
                              1 => "0001000000000101",
                              2 => "0011000000000110",
                              3 => "0111000000000001",
                              4 => "0000000000001100",
                              5 => "0000000000000011",
                              6 => "0000000000000000",
                              others => (others => '0'));
begin
  -- Concurrent code
end Behavioral;

But you may want to look at the specific FPGA and tool features to see if there is some specific way that initialization values should be given to the RAM in so the synthesis tool can map it correctly.