is there a tool or script somewhere that allows me to parse Verilog files to obtain the names of the inputs and outputs of the module? i tried to look at iverilog and yosys but they do not seem to have this feature. i can write my own but i do not want to reinvent the wheel. thanks!
Verilog-Perl can parse Verilog to obtain the names of the inputs and outputs of the module. It is free software which can be downloaded and installed. There are many code examples to do what you want, but it does require some knowledge of the Perl language. You are wise to not want to reinvent this wheel.