When I set a pin in 'Z' state it keeps the state it has before.
For example:
if rising_edge(Clock) then
counter <= counter + 1;
case counter is
when 0 =>
PIN <= '0';
when 1 =>
PIN <= 'Z';
others =>
end case;
end process;
If I execute this code I'll have PIN set at '0' in 'Z' state.
if rising_edge(Clock) then
counter <= counter + 1;
case counter is
when 0 =>
PIN <= '1';
when 1 =>
PIN <= 'Z';
others =>
end case;
end process;
If I execute this code I'll have PIN set at '1' in Z state.
What I need is to have PIN set to '0' in Z state regardless of the state it was before. But I need to accomplish this without using an additional clock cycle to set PIN from '1' to '0' and then to 'Z'. Is that possible?
If you need an FPGA pin to be tristated, but also have a pulldown, you must set up the pulldown in your toolchain's pin configuration tool. I'm not aware of any FPGA toolchain that will infer a pulldown from assignment to 'L'
, which appears to be what you want (tristate with pulldown seems equivalent to 'weak low'). If you are running simulation only, try setting PIN <= 'L'
.