I have a VHDL package that defines a function (forward declaration) and a constant. The constant's value is calculated by that function, whose body is located in the package body.
As of now ModelSim/QuestaSim is the only tool that does not like this code. It needs 2 packages so the body was parsed before the constant declaration.
package test is
function mytest(param : boolean ) return boolean;
constant value : boolean := mytest(TRUE);
end package;
package body test is
function mytest(param : boolean ) return boolean is
begin
return not param;
end function;
end package body;
Is this not allowed in VHDL and other tools use relaxed parsing rules, or is that a ModelSim issue?
With a deferred constant, and assign in package body after mytest function is elaborated, it is possible even in ModelSim:
package test is
function mytest(param : boolean ) return boolean;
constant value : boolean;
end package;
package body test is
function mytest(param : boolean ) return boolean is
begin
return not param;
end function;
constant value : boolean := mytest(TRUE);
end package body;
Handling across different tools appears to be inconsistent, since as you notice ModelSim requires the deferred constant, but Altera Quartus II allows assign of constant before function elaboration, thus without deferred constant.
The VHDL-2008 standards covers subprogram elaboration in:
14.4.2.1 General: ..., it is illegal to call a subprogram before its corresponding body is elaborated.
Effect of subprogram body elaboration is described in:
14.4.2.2 Subprogram declarations, bodies, and instantiations: ... Elaboration of a subprogram body, other than the subprogram body of an uninstantiated subprogram, has no effect other than to establish that the body can, from then on, be used for the execution of calls of the subprogram.