How can generate the 32-bit RISCV form chisel soure. What are the required modifications?

Question

According to the RISCV toolchain, we are generating the verilog files for Rocketchip as 64-bit. but we need 32-bit RISCV rocket chip. For that what are requirements and modifications in scala and chisel files.

Is it possible to generate the 32-bit Rocket core to do so.

Answer 1

Rocket is a RV64 implementation. Unfortunately it does not have a simple switch to make it RV32. Making it RV32 will require some modification, hopefully small.