I am creating some IP than runs the template of an algorithm. Basically I have designed it so that the VHDL is parameterisable for any fixed-point data representation, with GENERICS, D_WIDTH and FRAC.
I am using Xilinx IP cores for the arithmetic, so hence I need to leave these parameterisable for changes in D_WIDTH when using the IP. I want to leave these as Black Boxes so they are then externally defined. But in the attribute definition can the widths be variable e.g.
ATTRIBUTE BLACK_BOX_PAD_PIN OF sub_dsp : COMPONENT IS "A[31:0],B[31:0],CLK,CE,SCLR,S[31:0]";
The data widths are fixed to 32, and as described I need these to be variable as such:
ATTRIBUTE BLACK_BOX_PAD_PIN OF sub_dsp : COMPONENT IS "A[D_WIDTH-1:0],B[D_WIDTH-1:0],CLK,CE,SCLR,S[D_WIDTH-1:0]";
would this work? Or is there another method I can integrate parameterisable IP into my own IP!?
Thanks Sam
I think this would work:
ATTRIBUTE BLACK_BOX_PAD_PIN OF sub_dsp : COMPONENT IS "A[" & integer'image(D_WIDTH-1) & ":0],B[" & integer'image(D_WIDTH-1) & ":0],CLK,CE,SCLR,S[" & integer'image(D_WIDTH-1) & ":0]";
There may be other ways to deal with this. Some Xilinx IP cores are "clear-source", so you can add the sources to your project and instantiate them as if it were your code. You loose GUI parametrization and tool management of update though.
Depending on your algorithm, you could use a max width for Xilinx's IP cores and map smaller D_WIDTH to the lsb of the IP. This works well if Xilinx's optimization mechanisms trim unused bits out of the design, which largely depends on the operation you perform.
You can also use generic in your code for all D_WIDTH, but that gets real ugly real fast.