initializing memory in VHDL

I have this piece of code:

type mem_type is array (0 to 15) of std_logic_vector (15 downto 0); 
signal Mem : mem_type:= (X"269F",X"351A",X"7752",X"9152",
                         X"CCD1",X"7A8B", "A429",X"5758",
                         X"A325",X"BC3D",X"725D",X"B459",
                         X"7264",X"E241",X"74FC",X"19BC");

I am getting the following error at the line where I am initializing Mem:

No array or record type can be found that has elements of types matching the aggregate.

Solution

One of your initialisation values doesn't have an X before it to specify a hex value. Your code is then trying to put a string into a 16-bit std_logic_vector, which is of course an error.

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