how to connect output signal of one module to input signal of other module

Suppose my VHDL code is like this:

entity x1:
port(a: out std_logic;
....
....
);
architecture behv1 of x1 is
....
end behv1;

entity y1 
port(b: in std_logic;
....
....
);
architecture behv1 of y1 is
begin
m1: x1 port map(a=>b);    
end behv1;

So, here a is the output signal of entity x1 which is connected directly to input b of other entity y1.

Solution

You're kinda going about it in the wrong way.

entity y1 provides the interface of the y1 entity. It specifies that you have an input to the entity, b. This means that you can read the value of b from inside your architecture declaration. You should then implement what you want your y1 module to do inside architecture behav1.

From what I understand though, you want to instantiate an x1 and a y1, then connect them together. To do this, you need to provide an implementation of x1 and y1, and then instantiate both in a separate top-level and connect them together. Something like this:

entity x1:
port(a: out std_logic;
....
....
);
architecture behv1 of x1 is
    -- Do something...
end behv1;

entity y1 
port(b: in std_logic;
....
....
);
architecture behv1 of y1 is
begin
    -- Do something...    
end behv1;

entity toplevel
port (
    clk : in std_logic;
    ...
);
architecture toplevel_arch of toplevel is
    signal x1_output : std_logic; -- Temp to connect both modules
begin
    m_x1: x1 port map(a => x1_output);
    m_y1: y1 port map(b => x1_output);
end toplevel_arch;