how to solve "symbol does not have visible declaration error"

My vhdl code is as follows:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity pc is
port( inp : in std_logic_vector(31 downto 0);
  oup : out std_logic_vector(31 downto 0));
end pc ;

architecture behv of pc is
signal programcounter : std_logic_vector(31 downto 0);
begin
process(inp)
begin
programcounter<=inp;
oup<=programcounter;
end process;
end behv;

library ieee;
use ieee.std_logic_1164.all;

entity ins_memory is
port( inp1 : in std_logic_vector(31 downto 0);
  oup1 : out std_logic_vector (4 downto 0));

end ins_memory;

architecture behv1 of ins_memory is
type ROM_Array is array (0 to 14)
of std_logic_vector(4 downto 0);
constant Content: ROM_Array := (
0 => "00001",
-- Suppose ROM has
1 => "00010",
-- prestored value
2 => "00011",
-- like this table
3 => "00100",
--
4 => "00101",
--
5 => "00110",
--
6 => "00111",
--
7 => "01000",
--
8 => "01001",
--
9 => "01010",
--
10 => "01011",
--
11 => "01100",
--
12 => "01101",
--
13 => "01110",
--
14 => "01111",
--
OTHERS => "11111"
--
);

component pc is
port( inp : in std_logic_vector(31 downto 0);
  oup : out std_logic_vector(31 downto 0));
end component ;

begin
D1: pc port map(inp1);
process(inp1)
begin
oup1<= Content (to_integer(inp1));
end process;
end behv1;

Here basically, I am trying to instantiate pc in entity ins_memory which is a ROM

The error I am getting is :

oup1<= Content (to_integer(inp1)); The symbol 'TO_INTEGER' does not have a visible declaration.

so, How can I solve this error?

Solution

There are two entity/architecture declarations, but only the first uses std_logic_arith/unsigned packages, thus these are not known to the second. So add it before ins_memory the entity:

use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Next, the to_integer is from the numeric_std package. The std_logic_vector to integer convert in the std_logic_unsigned package is named conv_integer, so update the oup1 assign to:

oup1<= Content (conv_integer(inp1));

Btw, you can get ridge of the component declaration if you instantiate the pc entity directly with:

D1 : entity work.pc port map(inp1);

Another btw., consider using the VHDL standard numeric_std package instead of the proprietary Synopsys std_logic_arith/unsigned packages.