VHDL Is there a cleaner way to set specific bit, given the bit number?

Question

Given a bit number, I am trying to set that bit in a std_logic_vector. This is for toggling various clock outputs one at a time.

First of all, I've completely given up on sll, or SHIFT_LEFT which seems to be the obvious way to do it, but which totally doesn't work at all.

variable v_cmd_clk_1: std_logic_vector(11 downto 0);

...

--- set bit number "s_proc_chan", plus 4, in v_cmd_clk_1
v_cmd_clk_1 := "0000" & "0000" & "0000";
v_cmd_clk_1( to_integer ( unsigned(s_proc_chan(2 downto 0))) + 4  ) := '1';

...
-- And then later on in the process assign it to an actual signal
cmd_clk <= v_cmd_clk_0;

Is there a better or cleaner syntax for doing this?

Thanks.

Answer 1

Three suggestions for you. First one uses aggregates:

v_cmd_clk_1 <= (to_integer(unsigned(s_proc_chan(2 downto 0)))+4) => '1', others => '0');

Second one uses integer to unsigned conversion:

v_cmd_clk_1 <= std_logic_vector(to_unsigned(2**(to_integer(unsigned(s_proc_chan(2 downto 0)))+4)); -- No guarantee on parentheses matching

Third one, using shift_left:

v_cmd_clk_1 <= std_logic_vector(shift_left(resize(unsigned'("1"), v_cmd_clk_1'length), to_integer(unsigned(s_proc_chan(2 downto 0)))+4));