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"when others" line in VHDL case statement?

I'm a student learning VHDL and the example code from my textbook shows lines similar to the following in several places;

when "000" => tmp_result <= a and b;
when "001" => tmp_result <= a or b;
...
when others => tmp_result <= (others => '0');

I find the syntax of VHDL very unintuitive overall, but I really don't "get" this line at all.

I'm really confused why the above line isn't just:

when others => tmp_result <= '0'

Why is it like that?

I've tried Googling but haven't been able to find an explanation.

Solution

  • STD_LOGIC_VECTOR has a fixed size. So, when you are assigning a value to it, instead of defining each bit explicitly, you can just use

    (others => '0')

    to denote you want the remaining bits to be set to 0. Since the variable has a fixed size, your compiler will know how many bits to set. You could mix this with a bunch of other statements, e.g. 

    tmp_result <= (1=>'1', OTHERS => '0');

    A circumstance where it could come in handy is this:

    ENTITY test IS
    GENERIC (n : INTEGER := 7);
    PORT (a : OUT STD_LOGIC_VECTOR (n DOWNTO 0)
          );
END test;

    You see, we may have to change the size each time and that's why we are defining a generic variable. Using (others => '0') to set it to 0 will save us from having to change the whole program all over again.