Why are ports redefined when using components?

I'm learning VHDL and find something confusing. Suppose you have the following entity:

entity alu32 is
    port(a, b       : in STD_LOGIC_VECTOR(31 downto 0);
         alucontrol : in STD_LOGIC_VECTOR(2 downto 0);
         result     : buffer STD_LOGIC_VECTOR(31 downto 0);
         zero       : out STD_LOGIC);
end alu32;

When using it as a component in another entity's architecture, it's defined like this:

component alu32
  port(
        a, b       : in STD_LOGIC_VECTOR(31 downto 0);
        alucontrol : in STD_LOGIC_VECTOR(2 downto 0);
        result     : buffer STD_LOGIC_VECTOR(31 downto 0);
        zero       : out STD_LOGIC
    );
 end component;

My question is, why do we redefine the port? It seems like a pointless exercise since it's exactly the same as in the entity declaration. Why wasn't VHDL design to allow you to simply use a component like this:

component alu32;

Solution

You can, since VHDL-93. You can instantiate using

Alu_0: entity work.alu32
port map (
    ...
);

In this snippet, you can replace work for the VHDL library of the component you want to instantiate, work is always the current library the VHDL source resides in.

Why use the component declaration? First, they are required if what you want to instantiate is not VHDL, such as Verilog, IP cores and netlist. Second, using configuration allow to change port/entity binding, but you need component declaration for that.