VHDL & Synthesizing w/Quartus simple error

So I'm currently trying to synthesize a design and apparently it's too big to compile or something. It compiles and simulates perfectly in ModelSim, but in quartus throws this error:

Error: Design requires 491 I/O resources -- too many to fit in 456 available in the selected device or any device in the device family

Apparently I have 491 I/O resources but can only fit 456 (??). I have no idea what that means or how to extend the 456 number. Google searching gets me nowhere. Does anybody know what to do in this case?

Thanks a lot!

Solution

you may try virtual pins assignements:

http://quartushelp.altera.com/13.1/mergedProjects/logicops/logicops/def_virtual_pin.htm

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