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verilogxilinx-ise

How to constrain a counter reg size in verilog for ise synthesis?


I want to declare a counter reg in function of some parameters. I did it in this way :

parameter clk_freq = 95000; // clock frequency in kHz
parameter debounce_per_ms = 20;
localparam MAX_COUNT = ((debounce_per_ms * clk_freq)) + 1;
reg [$ln(MAX_COUNT)/$ln(2):0] count;

This work well in simulation with icarus but ISE 14.7 don't want to synthesize it. That give this error:

WARNING:HDLCompiler:1499 - "/src/button_deb.v" Line 4: Empty module <button_deb> remains a black box.

If I define the count like this :

reg [22:0] count;

ISE synthesize it well. If someone have a clue ?


Solution

  • This worked for me, although I'd swear I used functions like $log, $log10, $ceil and the like in the past with no problems.

    module param_with_log2 (
        input wire clk,
        output wire d
        );
    
        function integer log2;
            input integer value;
            begin
                value = value-1;
                for (log2=0; value>0; log2=log2+1)
                    value = value>>1;
            end
        endfunction
    
        parameter clk_freq = 95000; // clock frequency in kHz
        parameter debounce_per_ms = 20;
        localparam MAX_COUNT = ((debounce_per_ms * clk_freq)) + 1;
        localparam integer UPPER = log2(MAX_COUNT);
    
        reg [UPPER:0] count;
        always @(posedge clk)
            count <= count + 1;
        assign d = count[UPPER];
    endmodule
    

    XST seems to have a problem with using constant functions: they only can be at the right side of a parameter declaration expression (as I suggested in my first comment). Credits and more information here: http://www.beyond-circuits.com/wordpress/2008/11/constant-functions/

    Notice too that UPPER is declared as localparam integer so we can use it inside a register definition upper bound expression. Credits go to the owner of this post: http://forums.xilinx.com/t5/Synthesis/XST-and-clog2/m-p/244440/highlight/true#M6609

    (the module is just a phony module to have something that I can symthesize without the fear that the synthesizer will wipe all my code. It doesn't perform any kind of debouncing)