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vhdlfpgamodelsimintel-fpga

VHDL integer range inclusive? Difference in FPGA vs. simulation

I'm new to FPGAs. I've been doing some simple tests and I found an issue I don't fully understand.

I have a 50MHz clock source.

I have a signal defined as:

SIGNAL ledCounter : integer range 0 to 25000000 := 0;

When the ledCounter reaches 25,000,000 I toggle an LED and reset the counter. This works great directly on the FPGA.

IF (rising_edge(CLK)) THEN
    ledCounter <= ledCounter + 1;

    IF (ledCounter = 25000000) THEN
        ledCounter <= 0;
        toggle <= not toggle;
        LED(0) <= toggle;
    END IF;
END IF;

When running inside ModelSim I get an error when the counter reaches 25000000. For it to run in the simulator I have to define the range as:

SIGNAL ledCounter : integer range 0 to 25000001 := 0;

Does anyone have any insight into why this is happening? The code runs on the FPGA well but won't run in the simulator without the above modification.

EDIT: The modelsim error is nondescriptive: Cannot continue because of fatal error. HDL call sequence. Stopped at C:/Users/robert/Documents/fpga/testsim/test.vhd 20 Process line__17

Solution

  • This happens because the line ledCounter <= ledCounter + 1 happens before the comparaison. Even if ledCounter's value won't actually reach 25000001, since overridden by the following statements, at this point it is scheduled to reach it, causing the simulation error. You can solve it easily by moving the increment in an else branch:

    IF (rising_edge(CLK)) THEN
    IF (ledCounter = 25000000) THEN
        ledCounter <= 0;
        toggle <= not toggle;
        LED(0) <= toggle;
    ELSE
        ledCounter <= ledCounter + 1;
    END IF;
END IF;

    That way, ledCounter is never scheduled to be 25000001 and no error will occur. Notice that both code behave exactly the same.