I'm new to the world of VHDL and I'm getting this error saying Syntax error near process. I checked for the solutions and found that there may be a missing end if statement but in my code I'm not having that problem.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
use STD.textio.all;
entity Main_Architecture is
port(
SEN: out std_logic;
reset: in std_logic;
clk: in std_logic
);
end Main_Architecture;
architecture Behavioral of Main_Architecture is
signal main_counter : std_logic_vector(7 downto 0) := "00000000";
signal mux: std_logic_vector(1 downto 0) := "00";
signal output : std_logic_vector(7 downto 0);
signal main_counter_int : integer range 0 to 127:=0;
signal main_generator : std_logic_vector(7 downto 0);
begin
process(main_counter,reset,clk)
variable x: std_logic;
variable y: std_logic;
variable z: integer;
begin
if(reset = '1') then
main_counter <= (others => '0');
end if;
if(clk'event and clk='1') then
if(mux="00") then --load main counter
y:= main_counter(0);
x:= (main_counter(0)XOR main_counter(6) XOR main_counter(7));
main_counter(7 downto 1) <= main_counter(6 downto 0);
main_counter(0)<=x;
main_counter <= main_counter+'1';
output(0)<=y;
output(1)<=main_counter(0);
output(2)<=main_counter(1);
output(3)<=main_counter(2);
output(4)<=main_counter(3);
output(5)<=main_counter(4);
output(6)<=main_counter(5);
main_counter_int<=conv_integer(output);
if(main_counter >= "11111111") then
mux <= "01";
end if;
end if;
if(mux="01") then
if(main_counter_int < 2) then
z:=1;
else if(main_counter_int < 4) then
z:=2;
else if(main_counter_int < 8) then
z:=3;
else if(main_counter_int < 16) then
z:=4;
else if(main_counter_int < 32) then
z:=5;
else if(main_counter_int < 64) then
z:=6;
else if(main_counter_int < 128) then
z:=7;
end if;
end if;
end if;
end process; -------- LINE 104 -------
end Behavioral;
Also I want to create a std_logic_vector which has a size from value z to 0. i.e. A vector of size z+1. How can i make it?
Without looking into any other issues in your code, I think the problem is this section, which I have re-formatted to show how many 'end if' statements you are missing:
if(mux="01") then
if(main_counter_int < 2) then
z:=1;
else
if(main_counter_int < 4) then
z:=2;
else
if(main_counter_int < 8) then
z:=3;
else
if(main_counter_int < 16) then
z:=4;
else
if(main_counter_int < 32) then
z:=5;
else
if(main_counter_int < 64) then
z:=6;
else
if(main_counter_int < 128) then
z:=7;
end if;
end if;
I think you probably wanted to use elsif instead of else if.
For the second part of your question, assuming you want to produce code that can be realised in hardware, there is no such thing as a run-time sized std_logic_vector. The best you can do is to make your vector have the maximum size that it could need, then only assign or use parts of it, based on the value of 'z'.
USE ieee.std_logic_arith.ALL;
This is not a 'true' standard library, and there are many other answers where people recommend against using this library. If you need to perform math functions (e.g. +), USE ieee.numeric_std.all;, then create signals of type signed or unsigned. In your example, main_counter would be declared signal main_counter : unsigned(7 downto 0) := "00000000";. Operations like + can then be performed on this signal, with no ambiguity as to whether it is supposed to be signed or not.
Lastly, the section:
output(0)<=y;
output(1)<=main_counter(0);
output(2)<=main_counter(1);
output(3)<=main_counter(2);
output(4)<=main_counter(3);
output(5)<=main_counter(4);
output(6)<=main_counter(5);
could more compactly be written using the concatenation operator & as
output(6 downto 0) <= main_counter(5 downto 0) & y;
Side note: output(7) doesn't seem to ever be assigned.