I'm getting the following error in ModelSim:
Error: [..]/test1_toVectorAlignment_rtl.vhd(40): Ambiguous type in infix expression; t_RAMXx8 or ieee.std_logic_1164.STD_LOGIC_VECTOR.
ARCHITECTURE rtl OF test1_toVectorAlignment IS
type t_RAMXx8 is array (natural RANGE <>) of std_logic_vector(7 downto 0);
signal RAM28x8: t_RAMXx8(0 to 27);
BEGIN
...
currentIq<=unsigned(RAM28x8(5)(4 downto 0) & RAM28x8(4));
...
END rtl;
Entity declaration:
ENTITY test1_toVectorAlignment IS
...
currentIq: out unsigned(12 downto 0);
...
END test1_toVectorAlignment;
Can someone tell me with this information how I can solve this problem?
The problem sometimes with arrays of vectors is that the compiler doesn't know if you intend to concatenate two vectors into a single vector, or two vectors into a 2-vector array. You need to tell it what you're intending to concatenate as:
currentIq <= unsigned(std_logic_vector'(RAM28x8(5)(4 downto 0) & RAM28x8(4)));
In this case, since unsigned does not have any such ambiguity in the code you've posted, you could also get away with this shortcut:
currentIq <= unsigned(RAM28x8(5)(4 downto 0)) & unsigned(RAM28x8(4));
But the first method is safer, and better.
A little more explanation:
If you were assigning the result of that concatenation to a signal of type std_logic_vector, there would be no problem, as the concatenation result type would be unambiguous. The problem here specifically is that you are also typecasting in the same expression, so the compiler can't assume what "intermediate" type you wish to concatenate into, even if it's obvious to you that there's only one reasonable choice.