How 16 bit array needs 5 bit address (Xilinx Vivado HLS)?

Question

I am novice in Xilinx HLS. I am following tutorial ug871-vivado-high-level-synthesis-tutorial.pdf(page 77).

The code is

#define N 32

void array_io (dout_t d_o[N], din_t d_i[N])     
{   
   //..do something
}

After synthesis, I got report like

I am confused that how the width of the address port has been automatically sized match to the number of addresses that must be accessed (5-bit for 32 addresses)?

Please help.

Answer 1

From the UG871, it seems that the size of the array is from 0 to 16 samples, hence you need 32 addresses to access all values (see Figure 69). I guess that the number N is somewhere limited to be less than 32 (or be exactly 16). This means that Vivado knows this limitation, and generates only as many address bits as are needed. Most synthesis tools check the constraints on size and optimize unnecessary code away.