So I have the following VHDL code to implement an Nbit adder/subtractor using only a 2:1 mux, an inverter (flips bit), and a full adder. I am having issues connecting the carry out of an adder to the next ones carry in while having the first adder have a carry in of i_Control. Any help would be greatly appreciated :).
library IEEE;
use IEEE.std_logic_1164.all;
use work.all;
entity add_subtract is
generic(N : integer := 16);
port(i_M : in std_logic_vector(N-1 downto 0);
i_N : in std_logic_vector(N-1 downto 0);
i_Control : in std_logic_vector(N-1 downto 0);
o_S : out std_logic_vector(N-1 downto 0));
end add_subtract;
architecture structure of add_subtract is
component bit_adder
port(i_X : in std_logic;
i_Y : in std_logic;
i_Cin : in std_logic;
o_Ss : out std_logic;
o_Couts : out std_logic);
end component;
component inverter
port(i_A : in std_logic;
o_F : out std_logic);
end component;
component bit_mux
port(i_X : in std_logic;
i_Y : in std_logic;
i_S : in std_logic;
o_N : out std_logic);
end component;
signal compvalue, muxvalue, addervalue : std_logic_vector(N-1 downto 0);
signal sel, carry : std_logic_vector(N-1 downto 0);
signal k : integer := 0;
begin
carry(0) <= i_Control(0);
G1: for i in 0 to N-1 generate
one_comp: inverter
port map(i_A => i_N(i),
o_F => compvalue(i));
mux: bit_mux
port map(i_X => i_N(i),
i_Y => compvalue(i),
i_S => i_Control(i),
o_N => muxvalue(i));
struct_adder: bit_adder
port map(i_X => i_M(i),
i_Y => muxvalue(i),
i_Cin => carry(i),
o_Ss => o_S(i),
o_Couts => carry(i));
end generate;
end structure;
Make the carry array one longer:
signal carry : std_logic_vector(N downto 0); -- was N-1
and change this:
o_Couts => carry(i));
to this:
o_Couts => carry(i+1));
in your generate statement while leaving the i_Cin carry input association as is.
If the last carry out isn't conveyed through an output port the net will get eaten during synthesis.