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How to determine if more than one bit in an STD_LOGIC_VECTOR is set in VHDL

I am wondering how I can determine if more than one bit of a four-bit STD_LOGIC_VECTOR is set to '1'.

e.g if it is "1001" or "1100" or "1111".

I am writing a program where I have to set an error signal to '1' if I get more than one control signal to my entity. The four control signals have been merged into one 4-bit STD_LOGIC_VECTOR and I need a smart way to determine if more than one of the bits are set.

Solution

  • I solved it with

    with selvec select
ERR <=  '0' when "0001",
        '0' when "0010",
        '0' when "0100",
        '0' when "1000",
        '0' when "0000",
        '1' when others;

    Not the neatest code but it does the trick.