VHDL Signal Assignment Confusion

I was studying VHDL and came across a question for which I could not find an answer. I understand the below example and why the result is 7:

architecture SIGN of EXAMPLE is
  signal TRIGGER, RESULT: integer := 0; 
  signal signal1: integer :=1;
  signal signal2: integer :=2;
  signal signal3: integer :=3;
begin

  process 
  begin
    wait on TRIGGER;
    signal1 <= signal2;
    signal2 <= signal1 + signal3;
    signal3 <= signal2;
    RESULT <= signal1 + signal2 + signal3;
  end process;

end SIGN;

However, what happens if I put signal1 in the sensitivity list? Or all of the signals?

Solution

First, if a sensitivity list is created for the process, then the wait on TRIGGER statement must be removed or commented out, since a process with sensitivity list can't also have wait statements.

If signal1 is the process sensitivity list, then the process is initially run and then re-run as long as there are changes to the signal1.

The values after default assing, or based on assign in process run, are for signal1, signal2, signal3, and RESULT:

Default.:  1,  2,  3,  0
First...:  2,  4,  2,  6
Re-run 1:  4,  4,  4,  8
Re-run 2:  4,  8,  4, 12

Remember that signal assign does not take effect until after the process has finished, based on the delta cycle simulation model.

Since there is no change in signal1 between re-run 1 and 2, then the process is not run any more, and the value of RESULT is thus 12, as from the last run.

If signal1 and signal2 are in the process sensitivity list, then each process run will alter one of the signals, thus the process will continue to rerun until the simulator delta cycle iteration limit is reached or an out of range value will occur for the integer data type, resulting in no further change of the value.