I try to simulate a very very simple .vo file,the output of quartus compilation, I attached my code, .v file and quartus output .vo file. For simulating modelsim-altera is used. After trying for running simulation following error appeared on screen. How can i fix this?
Thanks
CA.v :
module CA (input a , b, output c);
assign c = a + b;
endmodule
CA.vo :
// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// VENDOR "Altera"
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 14.0.0 Build 200 06/17/2014 SJ Full Version"
// DATE "12/16/2014 07:07:50"
//
// Device: Altera EP4CE6E22C8 Package TQFP144
//
//
// This Verilog file should be used for ModelSim-Altera (Verilog) only
//
`timescale 1 ps/ 1 ps
module CA (
a,
b,
c);
input a;
input b;
output c;
// Design Ports Information
// c => Location: PIN_30, I/O Standard: 2.5 V, Current Strength: Default
// a => Location: PIN_31, I/O Standard: 2.5 V, Current Strength: Default
// b => Location: PIN_32, I/O Standard: 2.5 V, Current Strength: Default
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;
tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("CA_v.sdo");
// synopsys translate_on
wire \c~output_o ;
wire \b~input_o ;
wire \a~input_o ;
wire \Add0~0_combout ;
// Location: IOOBUF_X0_Y8_N16
cycloneive_io_obuf \c~output (
.i(\Add0~0_combout ),
.oe(vcc),
.seriesterminationcontrol(16'b0000000000000000),
.devoe(devoe),
.o(\c~output_o ),
.obar());
// synopsys translate_off
defparam \c~output .bus_hold = "false";
defparam \c~output .open_drain_output = "false";
// synopsys translate_on
// Location: IOIBUF_X0_Y6_N15
cycloneive_io_ibuf \b~input (
.i(b),
.ibar(gnd),
.o(\b~input_o ));
// synopsys translate_off
defparam \b~input .bus_hold = "false";
defparam \b~input .simulate_z_as = "z";
// synopsys translate_on
// Location: IOIBUF_X0_Y7_N1
cycloneive_io_ibuf \a~input (
.i(a),
.ibar(gnd),
.o(\a~input_o ));
// synopsys translate_off
defparam \a~input .bus_hold = "false";
defparam \a~input .simulate_z_as = "z";
// synopsys translate_on
// Location: LCCOMB_X1_Y7_N0
cycloneive_lcell_comb \Add0~0 (
// Equation(s):
// \Add0~0_combout = \b~input_o $ (\a~input_o )
.dataa(\b~input_o ),
.datab(gnd),
.datac(gnd),
.datad(\a~input_o ),
.cin(gnd),
.combout(\Add0~0_combout ),
.cout());
// synopsys translate_off
defparam \Add0~0 .lut_mask = 16'h55AA;
defparam \Add0~0 .sum_lutc_input = "datac";
// synopsys translate_on
assign c = \c~output_o ;
endmodule
qsim output:
vsim -L cycloneive work.CA
# vsim -L cycloneive work.CA
# Loading work.CA
# ** Error: (vsim-10000) /home/bijan/Project/Quartus/CA5/simulation/modelsim/CA.vo(76): Unresolved defparam reference to '\c~output ' in \c~output .bus_hold.
# Region: /CA
# ** Error: (vsim-10000) /home/bijan/Project/Quartus/CA5/simulation/modelsim/CA.vo(77): Unresolved defparam reference to '\c~output ' in \c~output .open_drain_output.
# Region: /CA
# ** Error: (vsim-10000) /home/bijan/Project/Quartus/CA5/simulation/modelsim/CA.vo(86): Unresolved defparam reference to '\b~input ' in \b~input .bus_hold.
# Region: /CA
# ** Error: (vsim-10000) /home/bijan/Project/Quartus/CA5/simulation/modelsim/CA.vo(87): Unresolved defparam reference to '\b~input ' in \b~input .simulate_z_as.
# Region: /CA
# ** Error: (vsim-10000) /home/bijan/Project/Quartus/CA5/simulation/modelsim/CA.vo(96): Unresolved defparam reference to '\a~input ' in \a~input .bus_hold.
# Region: /CA
# ** Error: (vsim-10000) /home/bijan/Project/Quartus/CA5/simulation/modelsim/CA.vo(97): Unresolved defparam reference to '\a~input ' in \a~input .simulate_z_as.
# Region: /CA
# ** Error: (vsim-10000) /home/bijan/Project/Quartus/CA5/simulation/modelsim/CA.vo(113): Unresolved defparam reference to '\Add0~0 ' in \Add0~0 .lut_mask.
# Region: /CA
# ** Error: (vsim-10000) /home/bijan/Project/Quartus/CA5/simulation/modelsim/CA.vo(114): Unresolved defparam reference to '\Add0~0 ' in \Add0~0 .sum_lutc_input.
# Region: /CA
add library devicename_ver in library tab in start simulation window be sure to use only _ver (verilog) library otherwise you see the same error