I am not sure about an implementation. I've a multiplexer 8 input, 1 output and 3 select signal. One of these selects signal sequentialy acquires all value of a bit vector. Now I can choose 2 way.
The first way is to use another multiplexer where the input is the bit vector and the select signal is a counter log2 of the input.
The second way is to use a shift register and take the LSB bit of the vector.
What is the best solution in terms of area in a FPGA ?
Lets (for a incorrect start) assume that the FPGA only provides plain logical elements and flip-flops, and that the bit vector is N bits and holds the value while the used bit is selected, then the resources used by the two solutions are:
So this weights towards the mux solution, since the both needs almost the same number of 2-1 muxes due to the required initial loading of the N bit shift register, but the mux solution requires less flip-flops.
However, FPGAs depends heavily on LUTs which are usually based on small memory, and an additional feature is that these small memories can often be used as shift registers also. FPGAs with this feature allows LUT memory to be written directly, and then shifted, and this can be done without any 2-1 muxes for loading. So in this case the resources used for the shift solution are:
So the conclusion is that the best way to determine and achieve an optimal solution for an FPGA, is to know and utilize the feature of the specific target FPGA, and then try the implementing to be sure the synthesis tool maps the design correctly.