I am writing a dice or craps game using xilinx for a spartan-6 nexys 3 board.
I am getting these errors saying syntax error near 'if' or 'begin'. I know I have the correct libraries and I am confident I don't have any silly syntax error (though one can never be absolutely certain of this).
I am hoping an experienced VHDL composer can point me in the right direction as to where I am going wrong. Thank you in advance!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_bit.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity DiceGame is
Port ( Rb : in STD_LOGIC;
Reset : in STD_LOGIC;
CLK : in STD_LOGIC;
Sum : in integer range 2 to 12;
Roll : out STD_LOGIC;
Win : out STD_LOGIC;
Lose : out STD_LOGIC);
end DiceGame;
architecture DiceBehave of DiceGame is
signal State: integer range 0 to 5;
signal Nextstate: integer range 0 to 5;
signal Point: integer range 2 to 12;
signal Sp: STD_LOGIC;
begin
proces(Rb, Reset, Sum, State)
begin
Sp <= '0'; Roll<='0'; Win <='0'; Lose<='0';
case State is
when 0 =>
if Rb='1' then Nextstate <= 1;
end if;
when 1 =>
if Rb='1' then Roll='1';
elsif Sum=7 or sum=11 then Nextstate <= 2;
else if Sum=2 or Sum=3 or Sum=12 then Nextstate <= 3;
else Sp='1'; Nextstate <= 4;
end if;
when 2 =>
win <='1';
if Reset='1' then Nextstate <= 0;
end if;
when 3 =>
Lose <= '1';
if Reset='1' then Nextstate <=0;
end if;
when 4 =>
if Rb='1' then Nextstate <= 5;
--else NextState <=4;
end if;
when 5 =>
if Rb='1' then Roll='1';
elsif Sum = Point then Nextstate <=2;
elsif Sum= 7 then Nextstate <=3;
else Nextstate <=4;
end if;
end case;
end process;
Process(CLK)
begin
if CLK'event and CLK='1' then State<=Nextstate;
if Sp='1'then Point<= Sum;
end if;
end if;
end process;
end DiceBehave;
Here are my errors:
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 51: Syntax error near "begin".
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 54: Syntax error near "case".
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 58: Syntax error near "if".
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 63: Syntax error near "else".
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 64: Syntax error near "else".
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 65: Syntax error near "if".
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 69: Syntax error near "if".
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 70: Syntax error near "if".
ERROR:HDLCompiler:806 - "\\cdc-data\susers\lreves\Advanced Digital
WARNING:HDLCompiler:1369 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 91: Possible infinite loop; process does not have a wait statement
ERROR:HDLCompiler:854 - "\\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd" Line 43: Unit <dicebehave> ignored due to previous errors.
VHDL file \\cdc-data\susers\lreves\Advanced Digital Projects\DICEGAME\DiceGame\DiceBehave.vhd ignored due to errors
-->
Total memory usage is 221592 kilobytes
Number of errors : 15 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
Process "Synthesize - XST" failed
Line 51 misspelled process on Line 50 (will collapse the next errors on Lines 54, 58)
Line 63 Roll='1' should be Roll <= '1' (Will collapse errors lines 64, 65).
Line 69: else Sp ='1'; Nextstate <= 4; should be else Sp <= '1'; Nextstate <= 4;
Line 68: (not listed as an error) else if should be elsif
Line 88: (not listed as an error) then Roll = '1'; should be then Roll <= '1';
Then this analyzes and elaborates (and we make no claim it is correct, the urge to reformat indentation and whitespace is almost overwhelming).
(And these tells us you should use consistent indentation and whitepace to make these stand out).
Also note the only use clause that is necessary is
use IEEE.STD_LOGIC_1164.ALL;
The rest of those use clauses are noise.
(And here's hoping counting on my fingers and toes got the original line numbers right from your error messages and VHDL sample mismatching).