I have been writing the state machine for a traffic light controller.
-- Ampelsteuerung mit Zähler und FSM Componente
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity AMPLSTRG is
port ( CLK, B1, RES : in bit;
MAINRE, MAINYE, MAINGR : out bit;
FARMRE, FARMYE, FARMGR : out bit);
end AMPLSTRG;
architecture FUNKTION of AMPLSTRG is
type AMP_STATE is (S0, S1, S2, S3, S4, S5, S6, S7, S8); -- Typendefinition
signal SCLR : bit;
signal CYCLES : unsigned (4 downto 0);
signal STATE, NEXT_STATE : AMP_STATE; -- STATE = aktueller Status, NEXT_STATE nächster Status (Typenzuweisung)
begin
-- COUNTER Prozess
CO: process (CLK)
begin
if CLK = '1' and CLK'event then
if SCLR = '1' then
CYCLES <= (others => '0'); -- 'others' = gesamten Vektor auf '0' setzten
else
CYCLES <= CYCLES + 1;
end if;
end if;
end process CO;
AMP_SYNC: process (CLK, RES)
begin
if RES = '1' then
STATE <= S0 after 5 ns;
SCLR <= '1' after 5 ns;
elsif CLK = '1' and CLK'event then
STATE <= NEXT_STATE after 5 ns; -- Zustandszuweisung
end if;
end process AMP_SYNC;
AMP_KOMB: process (STATE, B1, CYCLES)
begin
-- default Werte Setzen
MAINRE <= '0' after 5 ns;
MAINYE <= '0' after 5 ns;
MAINGR <= '0' after 5 ns;
FARMRE <= '0' after 5 ns;
FARMYE <= '0' after 5 ns;
FARMGR <= '0' after 5 ns;
NEXT_STATE <= STATE;
SCLR <= '0';
case STATE is
when S0 => if B1 = '1' then
MAINGR <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
NEXT_STATE <= S1 after 5 ns;
SCLR <= '1' after 5 ns;
else -- MAINGR | FARMRE until B1 pressed
MAINGR <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
SCLR <= '1' after 5 ns;
end if;
when S1 => if CYCLES = '5' then
MAINGR <= '0' after 5 ns;
MAINYE <= '1' after 5 ns;
NEXT_STATE <= S2 after 5 ns;
SCLR <= '1';
else -- MAINGR | FARMRE for 5 sec
MAINGR <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
end if;
when S2 => if CYCLES = '5' then MAINRE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
NEXT_STATE <= S3 after 5 ns;
SCLR <= '1';
else -- MAINYE | FARMRE for 5 sec
MAINYE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
end if;
when S3 => if CYCLES = '2' then
MAINRE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
FARMYE <= '1' after 5 ns;
NEXT_STATE <= S4 after 5 ns;
SCLR <= '1';
else -- MAINRE | FARMRE for 2 sec
MAINRE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
end if;
when S4 => if CYCLES = '2' then
MAINRE <= '1' after 5 ns;
FARMGR <= '1' after 5 ns;
NEXT_STATE <= S5 after 5 ns;
SCLR <= '1';
else -- MAINRE | FARMRE | FARMYE for 2 sec
MAINRE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
FARMYE <= '1' after 5 ns;
end if;
when S5 => if CYCLES = '30' then
MAINRE <= '1' after 5 ns;
FARMYE <= '1' after 5 ns;
NEXT_STATE <= S6 after 5 ns;
SCLR <= '1';
else -- MAINRE | FARMGR for 30 sec
MAINRE <= '1' after 5 ns;
FARMGR <= '1' after 5 ns;
end if;
when S6 => if CYCLES = '5' then
MAINRE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
NEXT_STATE <= S7 after 5 ns;
SCLR <= '1';
else -- MAINRE | FARMYE for 5 sec
MAINRE <= '1' after 5 ns;
FARMYE <= '1' after 5 ns;
end if;
when S7 => if CYCLES = '2' then
MAINRE <= '1' after 5 ns;
MAINYE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
NEXT_STATE <= S8 after 5 ns;
SCLR <= '1';
else -- MAINRE | FARMRE for 2 sec
MAINRE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
end if;
when S8 => if CYCLES = '2' then
MAINGR <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
NEXT_STATE <= S0 after 5 ns;
SCLR <= '1';
else -- MAINRE | MAINYE | FARMRE for 2 sec
MAINRE <= '1' after 5 ns;
MAINYE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
end if;
end process AMP_KOMB;
end FUNKTION;
While compiling the code in Modelsim PE Student I get the following error:
No feasible entries for infix operator "="
After trying many different libraries I can't find any solution to fix this error. I guess it's a problem with the wrong library or the wrong use of the "=" operator.
Here is the full error report from Modelsim:
** Error: [...]/AMPSTR.vhdl(68): No feasible entries for infix operator "=".
** Error: [...]/AMPSTR.vhdl(68): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
** Error: [...]/AMPSTR.vhdl(78): No feasible entries for infix operator "=".
** Error: [...]/AMPSTR.vhdl(78): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
** Error: [...]/AMPSTR.vhdl(87): No feasible entries for infix operator "=".
** Error: [...]/AMPSTR.vhdl(87): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
** Error: [...]/AMPSTR.vhdl(98): No feasible entries for infix operator "=".
** Error: [...]/AMPSTR.vhdl(98): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
** Error: [...]/AMPSTR.vhdl(109): near "'": syntax error
** Error: [...]/AMPSTR.vhdl(114): near "else": expecting END or WHEN
** Error: [...]/AMPSTR.vhdl(117): near "if": expecting PROCESS
You're missing an
end case;
right before
end process AMP_KOMB;
You're using the wrong numeric package, because you're using bit types you should be using numeric_bit. You shouldn't be mixing std_logic_unsigned and numeric_xxx:
library ieee;
-- use ieee.std_logic_1164.all;
-- use ieee.std_logic_unsigned.all;
-- use ieee.numeric_std.all;
use ieee.numeric_bit.all;
The array length of CYCLES is 5, the index range (4 downto 0). The acceptable literals for use with it should be bit strings:
when S1 => if CYCLES = '5' then
should be:
when S1 => if CYCLES = "00101" then
etc. (every place CYCLES is evaluated). Note that '30' isn't a character literal, thirty in a bit string literal is "11110".
Fix all those and your VHDL design specification analyzes and elaborates. Without writing a test bench I didn't simulate it.
And after seeing Brian's answer it's worth pointing out that numeric_bit also has a type declaration for unsigned along with associated operators.