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VHDL code for turning 50MHz into 38KHz doesn't work

I'm having an issue with this code. Theoretically it should turn my 50MHz sign into 36KHz but as i run the simulation it turns out that the ir_38khz doesn't get any value it is unassigned.

Can you help me where i slip?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;

entity orajelKonverter is
    Port ( clk50 : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           ir_38khz : out  STD_LOGIC);
end orajelKonverter;

architecture Behavioral of orajelKonverter is

signal hz38_ctr : STD_LOGIC_VECTOR(9 downto 0);
signal s38 : std_logic;

begin

clk_generator : process (clk50, rst)

begin
    if rst = '1' then
        s38 <= '0';
        hz38_ctr <= (others => '0');

    elsif clk50='1' then

        if hz38_ctr = "1010010010" then
            hz38_ctr <= (others => '0');
            s38 <= not s38;
        else
            hz38_ctr <= hz38_ctr + "1";
        end if;
    end if;
end process clk_generator;

ir_38khz <= s38;

end Behavioral;

Here is the picture from the simulation: the problem itself

Solution

  • You need to initialize your signals to some value OR assert your reset to initialize them in simulation. I personally prefer #1, since signal initial conditions are synthesizable, despite the relatively common misconception that they are not. As a matter of fact, I avoid resets in my designs unless I absolutely need to use them. This is actually recommended by Xilinx. So for example you can do:

    signal s38 : std_logic := '0';

    This will guarantee that when your simulation starts it knows what to do with the line:

    s38 <= not s38;

    Previously the simulator was trying to do not U which is U.