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using non-linear lookup operation in VHDL


I want to take an 4-bit input and map it to an 4-bit output as defined by the substitution function.

Output <= Substitute(Input)

The substitution function can be implemented using a single table lookup operation utilising large memory components

A design requirement of our coprocessor is to provide fast hashing functions. Based on this fact we decide to implement a mechanism of improving the performance of the modified whirlpool hashing function.

The non-linear operations which are used in the hashing algorithm utilise a parallel 4-bit non-linear operation where the input nibble(4-bits) are mapped to another non-linear 4-bit value. All non- linear operations utilize only a single byte input.

The non-linear transforms which comprise SBox-1 and SBox-2 are given as 16 values of 4-bits input and there 16 values of 4-bits output For each SBox. The SBox-2 of the 16-bit input is used(LSB) and SBox-1(MSB) passed through to the output unaltered.

How can I implement case/select statement to do that?


Solution

  • This smacks of a homework assignment, but here is a sample entity using a with/select. With statements operate like case statements, but work in concurrent logic outside of a process. Case statements and if/elsif trees are typically used in sequential logic as they are only allowed inside a process.

    You could also create a constant array of 16 4-bit std_logic_vectors and index it using your 4-bit i value to get your o value. This may be even easier to read and understand, although it doesn't use any kind of with or case statement as you requested. Both syntactic formats would result in the same outcome after synthesis.

    This with statement will synthesize into 4x 4-input LUTs when given arbitrary output data as the literals to be assigned. Note that the output data (the left hand column of literals) will need to be changed to match your desired "non-linear mapping".

      library ieee;
      use ieee.std_logic_1164.all;
    
      entity example is 
        port(i : in std_logic_vector(3 downto 0);
             o : out std_logic_vector(3 downto 0)
            );
      end example;
    
      architecture behav of example is
      begin
    
        with i select
          o <= "1111" when "0000",
               "1110" when "0001",
               "1101" when "0010",
               "1100" when "0011",
               "1011" when "0100",
               "1010" when "0101",
               "1001" when "0110",
               "1000" when "0111",
               "0111" when "1000",
               "0110" when "1001",
               "0101" when "1010",
               "0100" when "1011",
               "0011" when "1100",
               "0010" when "1101",
               "0001" when "1110",
               "0000" when "1111",
               "XXXX" when others;
      end behav;